Difference between revisions of "Main Page"

Latest revision as of 09:10, 10 October 2025

General

• How to get best support from Verific
• Source code customization & Stable release services
• How to save computer resources (memory consumption & runtime)
• How do I know what language a Netlist in the netlist database comes from?
• What are the data structures in Verific?
• How do I remove all Verific data structures in memory?
• Does Verific build control and data flow graph (CDFG)?
• Does Verific support cross module references (XMR)?
• Are there options to control Verific software's behavior? Compile-time & run-time flags.
• How do I downgrade/upgrade messages from Verific? How do I get messages with more details?
• How do I tell the version of a Verific software release?
• Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)?
• How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"
• LineFile data from input files
• Difference between RTL and gate-level simulations - Flipflop with async set and async reset
• Preserving user nets - preventing nets from being optimized away
• Python pretty-printer for gdb
• Yosys-Verific integration
• How to enable long paths on Windows?

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

• Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
• Verilog: How do I get the list of included files associated with a Verilog source file?
• Verilog: How to get type/initial value of parameters.
• Verilog: Port Expressions
• Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
• Verilog: From the Verilog parsetree, how can I get the ports of a module?
• Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?
• Verilog: How do I get nested modules and get the library that contains the nested module?
• Verilog: How do I get linefile information of macro definitions?
• Verilog: How do I get port dimensions?
• Verilog: What is the order of binding modules to instances?
• Verilog: How Verific elaborator handles blackboxes/unknown boxes
• Verilog: Does Verific replace constant expressions with their respective values?
• Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?
• SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?
• SystemVerilog: Notes on analysis
• SystemVerilog: From the parsetree, how can I get the enums declared in a module?
• SystemVerilog: How do I identify packages being imported into a module?
• SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.
• SystemVerilog: Support for SystemVerilog top level module with interface ports.
• SystemVerilog: Parse tree node sharing in Static Elaboration.
• VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
• Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures
• Verilog/VHDL: How to prettyprint a parsetree node to a string.
• Verilog/VHDL: What does 'static elaboration' do?
• Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.
• Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?
• Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?
• Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?
• Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?
• Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?
• Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree
• Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?

Netlist Database

• Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?
• Netlist Database: Bit-blasting a multi-port RAM instance
• Netlist Database: System attributes

Output

• What language formats does Verific support as output?

Scripting languages: TCL, Perl, Python

• What programming languages can I use with Verific software?

Code examples

• Util/C++: How to use RegisterCallBackMsg()
• Util/C++: How to use MessageCallBackHandler Class
• Util/C++: How to use RegisterPragmaRefCallBack()
• Database/C++: Write out an encrypted netlist
• Database/C++: Extract clock enable
• Database/C++: Black box, empty box, and unknown box
• Database/C++: Post processing port resolution of black boxes
• Database/C++: Finding hierarchical paths of a Netlist
• Database/C++: Replacing Verific built-in primitives/operators with user implementations
• Database/Perl: Simple example of hierarchy tree elaboration
• Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)
• Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database
• Database/Verilog/C++: Memory elements of a RamNet
• Database/Verilog/C++: Process -f file and explore the Netlist Database
• Database/Verilog/Python: Process -f file and explore the Netlist Database
• Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database
• Database/Verilog/C++: Type Range example (simple)
• Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays
• Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id
• Verilog/C++: Simple examples of visitor pattern
• Verilog/C++: Statically elaborate with different values of parameters
• Verilog/C++: Prettyprint all modules in the design hierarchy
• Verilog/C++: Getting instances' parameters
• Verilog/C++: Accessing and evaluating module's parameters
• Verilog/C++: Visiting Hierarchical References (VeriSelectedName)
• Verilog/C++: Using stream input to ignore input file
• Verilog/C++: How to ignore certain modules while analyzing input RTL files
• Verilog/C++: How to tell if a module has encrypted contents
• Verilog/C++: Comment out a line using text-based design modification and parsetree modification
• Verilog/C++: How to use IsUserDeclared() : Example for port associations
• Verilog/C++: How to create new module in Verilog parsetree
• Verilog/C++: In Verilog parsetree adding names to unnamed instances
• Verilog/C++: How to get full hierarchy ID path
• Verilog/C++: How to traverse scope hierarchy
• Verilog/C++/Python: Getting design hierarchy from input RTL files
• Verilog/C++: How to access attributes in parsetree
• Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree
• Verilog/C++: How to get driving net of an instance
• Verilog/C++: Parse select modules only and ignore the rest
• Verilog/C++: Create DOT diagram of a parse tree
• Verilog/C++: How to evaluate a Verilog expression
• Verilog/C++: How to get parameters creation-time initial expression/value after Static Elaboration
• Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function
• Verilog/C++/Perl/Python: Where in RTL does it get assigned?
• Verilog/Perl: Access attributes of ports in parsetree and from netlist
• Verilog/C++: Evaluate 'for-generate' loop
• SystemVerilog/C++/Python: Retrieve package name for user-defined variable types
• SystemVerilog/C++: Pretty-print a module and the packages imported by the module
• SystemVerilog/C++: How to get packed dimensions of enum
• SystemVerilog/C++: How to replace a statement that has a label
• SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block
• VHDL/C++: Simple examples of VHDL visitor pattern
• VHDL/C++: Traverse instances in parsetree
• VHDL/C++: How to evaluate a VHDL expression
• Verilog/VHDL/C++: Parsing from data in memory

INVIO Code examples

• SystemVerilog/Python: Simple port modification