Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
 
(50 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
'''General'''
 
'''General'''
 +
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
Line 6: Line 7:
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
 
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
+
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
 
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
Line 30: Line 31:
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 +
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
 +
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
 
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
 
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
 
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
 
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 +
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
 +
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
'''Netlist Database'''
 
'''Netlist Database'''
 +
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
 +
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
 +
* [[System attributes | Netlist Database: System attributes]]
  
 
'''Output'''
 
'''Output'''
Line 44: Line 52:
  
 
'''Code examples'''
 
'''Code examples'''
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
+
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
 +
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 +
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 +
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
+
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++: Retrieve package name for user-defined variable types]]
+
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++/Python: Pretty-print a module and the packages imported by the module]]
+
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 +
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 +
* [[Type Range example with multi-dimensional arrays| Verilog/C++: Type Range example with multi-dimensional arrays]]
 +
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 +
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 +
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 +
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
 +
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 +
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 +
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 +
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 +
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 +
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 +
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 +
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Latest revision as of 12:58, 23 June 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples