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Showing below up to 126 results in range #1 to #126.

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1. A customer wants to analyze/elaborate
2. Access attributes in parsetree
3. Access attributes of ports in parsetree
4. Accessing and evaluating module's parameters
5. Bit-blasting a multi-port RAM instance
6. Buffering signals and ungrouping
7. Comment out a line using test-based design modification and parsetree modification
8. Comment out a line using text based design modification and parsetree modification
9. Compile-time/run-time flags
10. Constant expression replacement
11. Create DOT diagram of parse tree
12. Create a Netlist Database from scratch (not from RTL elaboration)
13. Cross-reference between the original RTL files and the elaborated netlist
14. Defined macros become undefined - MFCU vs SFCU
15. Design with System Verilog and Verilog 2001 files
16. Design with VHDL-1993 and VHDL-2008 files
17. Difference between RTL and gate-level simulations - Flipflop with async set and async reset
18. Does Verific build CDFG?
19. Does Verific support XMR?
20. Does Verific support cross
21. Does Verific support cross module references (XMR)?
22. Escaped identifiers in RTL files and in Verific data structures
23. Evaluate 'for-generate' loop
24. Extract clock enable
25. Fanout cone and grouping
26. Finding hierarchical paths of a Netlist
27. General
28. Getting instances' parameters
29. Hierarchy tree RTL elaboration
30. How do I know
31. How do I know what language a Netlist in the netlist database comes from?
32. How to change name of id in Verilog parsetree
33. How to check for errors in analysis/elaboration
34. How to create a Netlist database from scratch (not from RTL input)
35. How to create new module in Verilog parsetree
36. How to detect multiple-clock-edge condition in Verilog parsetree
37. How to find port dimensions
38. How to get all Verilog files being analyzed
39. How to get best support from Verific
40. How to get driving net of an instance
41. How to get enums from Verilog parsetree
42. How to get full hierarchy ID path
43. How to get library containing nested module
44. How to get linefile data of macros - Macro callback function
45. How to get linefile information of macro definitions
46. How to get module ports from Verilog parsetree
47. How to get packed dimensions of enum
48. How to get type/initial value of parameters
49. How to identify packages being imported into a module
50. How to ignore a (not used) parameter/generic in elaboration.
51. How to ignore certain modules while analyzing input RTL files
52. How to ignore parameters/generics in elaboration
53. How to insert/add a statement, or a module item, into a sequential block and a generate block
54. How to make lives easier
55. How to parse a string
56. How to replace a statement that has a label
57. How to tell if a module has encrypted contents
58. How to traverse scope hierarchy
59. How to use MessageCallBackHandler Class
60. How to use RegisterCallBackMsg()
61. How to use RegisterPragmaRefCallBack()
62. I'm using -v, -y,
63. I have a design consisting of
64. In Verilog parsetree adding names to unnamed instances
65. Included files associated with a Verilog source file
66. Instance - Module binding order
67. LineFile data from input files
68. Logic optimization across hierarchy boundaries
69. Macro Callback example
70. Memory elements of a RamNet
71. Message handling
72. Modules/design units with " default" suffix in their names
73. Modules with " 1", " 2", ..., suffix in their names
74. Modules with ' 1' ' 2' suffix in their names
75. Original RTL language
76. Output file formats
77. Parse select modules only and ignore the rest
78. Parsing from data in memory
79. Post processing port resolution of black boxes
80. Preserving user nets - preventing nets from being optimized away
81. Pretty-print a module and the packages imported by the module
82. Prettyprint all modules in the design hierarchy
83. Prettyprint to a string
84. Process -f file and explore the Netlist Database
85. Process -f file and explore the Netlist Database (C++)
86. Process -f file and explore the Netlist Database (py)
87. Python pretty-printer for gdb
88. Release version
89. Remove Verific data structures
90. Replacing Verific built-in primitives/operators with user implementations
91. Retrieve package name for user-defined variable types
92. Simple example of visitor pattern
93. Simple examples of VHDL visitor pattern
94. Simulation models for Verific primitives
95. Source code customization & Stable release services
96. Static elaboration
97. Statically elaborate with different values of parameters
98. Support IEEE 1735 encryption standard
99. SystemVerilog "std" package
100. System attributes
101. Tcl library path
102. Test-based design modification
103. Top level module with interface ports
104. Traverse instances in parsetree
105. Type Range example
106. Type Range example with multi-dimensional arrays
107. Using TypeRange table to retrieve the originating type-range for an id
108. Using stream input to ignore input file
109. VHDL, Verilog, Liberty, EDIF
110. Verific data structure
111. Verific data structures
112. Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path
113. Verilog/C++: How to use IsUserDeclared() : Example for port associations
114. Verilog/C++: How to use IsUserDeclared() and port associations
115. Verilog Port Expressions
116. Visiting Hierarchical References (VeriSelectedName)
117. What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
118. What are the data
119. What are the data structures in Verific?
120. What languages can I use with Verific software?
121. Where in RTL does it get assigned?
122. Where in RTL is it get assigned?
123. While looking at a Netlist
124. Why are the ports
125. Write out an encrypted netlist
126. Yosys-Verific Integration

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